EE+GS

Combination of Emotion Engine and Graphics Synthesizer used on some slim PS2 motherboards, in the Japan-only PSX DVR and in Japan/US launch model PS3 consoles. One of the first mass-produced 90nm ICs, as claimed by Sony. This claim is however disputed. Thanks to an old Sony press release, many details (of the first revisions; might have changed later on) are publicly known:

• EE: 128 bit RISC
• GS: Parallel rendering processor with embedded DRAM
• Process: 90 nm
• Total number of transistors: 53.5 million
• Embedded DRAM: 4 MB
• Memory size: 0.19 µm²
• Clock frequency: 294.912 Mhz
• Power consumption: 8 W (initial power consumption was 37 W two chips total)
• Metal layer: 5
• Die size: 86 mm² (initial die size was 413 mm² two chips total)
• Package: 536 pin EBGA

All revisions seem to be manufactured using the same process, as they all have an identical die area.

Revisions

• GS 1.12 + EE 4.2: CXD9797GB (some or all PSX first revision motherboard XPD-001, some GH-035-11, probably also on some XPD-005 or other GH-035 - ?)
  • 86 mm² die size with Toshiba's "CMOS4 90 nm" process
  • Produced 2003 - 2004
• GS 1.12 + EE 4.2: CXD9833GB (GH-035 - GH-052, XPD-005 (PSX), probably also on some XPD-001 (PSX), probably also on some PlayStation 3 COK-001 boards or prototypes since this revision is referenced in the PS3 service manual)
  • Apparently manufactured and used in parallel to CXD2953AGB
  • 86 mm² die size
  • Produced 2004 - 2007
• GS 1.13 + EE 4.2: CXD2953AGB (GH-035 - GH-052, probably also on some PSX boards XPD-001 or XPD-005, PlayStation 3 COK-001)
  • Apparently manufactured and used in parallel to CXD9833GB
  • 86 mm² die size
  • Produced 2004 - 2007

All revisions have a copyright date of 2003.

The 3 revisions seem to be externally interchangeable (at most maybe requiring some minimal changes to external circuitry, maybe not even requiring any changes at all), since all 3 of them can be found on the same board (GH-035).

For SCPH-790xx and newer PS2 consoles, GS was separated from EE again and EE was combined with IOP, SPU2 and RDRAM instead.